Semiconductor integrated circuit (IC, e.g., chip, die, etc.) is formed by many circuitry cells, and scan flip-flop is one of the most frequently adopted standard cells. Scan flip-flop may switch between a normal operation mode and a scan test mode; architecture of scan flip-flop may be equivalent to a multiplexer and an ordinary flip-flop circuit (e.g., a master-slave flip-flop). The multiplexer may have a data input terminal and a scan input terminal, and may respectively conduct the data input terminal and the scan input terminal to the flip-flop circuit during the normal operation mode and the scan test mode; hence, under triggering of a clock, the flip-flop circuit may latch and sample a signal which is selected to be conducted by the multiplexer; i.e., latch and sample data signal conducted from the data input terminal during the normal operation mode, and, on the other hand, latch and sample scan input signal conducted from the scan input terminal during the scan test mode.
To implement normal operation functions of an integrated circuit, the data input terminal of each scan flip-flop may be coupled to a logic block responsible for the normal operation functions; on the other hand, the scan input terminal may be coupled to an output terminal of another scan flip-flop, such that different scan flip-flops may be serially coupled as a scan chain for transmitting information related to a scan test. Please refer to FIG. 1 illustrating an architecture example of a typical digital circuit; this example may include two flip-flops FF[1] and FF[2], both are scan flip-flops; each flip-flop FF[.] may include terminals D, SI, SE, CK and Q, respectively as a data input terminal, a scan input terminal, a scan enabling terminal, a clock terminal and an output terminal. A terminal Q0 may be coupled to the terminal D of the flip-flop FF[1] via a logic block LOGIC[1], and a terminal Q1 from the terminal Q of the flip-flop FF[1] may be coupled to a subsequent flip-flop FF[2] via another logic block LOGIC[2], such that a data path of the normal operation mode may be established. On the other hand, to support the scan test mode, the terminal Q0 may be further coupled to the terminal SI of the flip-flop FF[1], and the terminal Q1 may be further coupled to the terminal SI of the flip-flop FF[2], such that a data path of the scan test mode, i.e., the scan chain, may be formed.
FIG. 1 also shows a typical architecture of a scan flip-flop, which includes transistors Tp1 to Tp6 (e.g., p-channel MOS transistors), transistors Tn1 to Tn6 (e.g., n-channel MOS transistors), and inverters 10a and 10b, 12a and 12b, 14a and 14b, as well as 16 and 18. The clock received by the terminal CK is inverted by the inverter 10a and outputted to a terminal CKB, and a clock at the terminal CKB is inverted by the inverter 18 and outputted to a terminal CKI; the signal at the terminal SE is inverted by the inverter 18 and outputted to a terminal SEB. The transistors Tp1 to Tp4 and Tn1 to Tn4 form a multiplexer 32. The transistors Tp5 to Tp6, Tn5 to Tn6, the inverters 12a and 12b, the inverters 12b and 14b controlled by the terminals CKI and CKB, as well as the inverter 16, collectively form a flip-flop circuit 34, which has a node 0 as an internal terminal, and outputs to the terminal Q. When the flip-flop FF[1] operates under the scan test mode, the terminal SE is raised to high level (logic 1), so the transistors Tn2 and Tp2 are turned on to conduct, and a voltage at the node n0 can therefore be controlled by the signal at the terminal SI, allowing the flip-flop circuit 34 to receive the signal from the scan chain; on the other hand, the transistors Tp3 and Tn3 are turned off and stops conducting. When the flip-flop FF[1] works under the normal operation mode, the terminal SE is pulled down to low level (logic 0), hence the transistors Tn3 and Tp3 are turned on; accordingly, a voltage at the node n0 can be controlled by the signal at the terminal D, allowing the flip-flop circuit 34 to receive the signal of normal operation; on the other hand, the transistors Tp2 and Tn2 are turned off.
In FIG. 1, a clock CKin is utilized to trigger the flip-flop circuits (e.g., the flip-flop circuit 34) of the flip-flops FF[1] and FF[2]. However, due to signal delays respectively introduced by the logic circuits LOGIC[1] and LOGIC[2], actual triggering clocks CK[1] and CK[2] respectively received at the terminals CK of the flip-flops FF[1] and FF[2] have be accordingly tuned, wherein delayers CTSD[1] and CTSD[2] respectively represent clock delays deliberately introduced by clock tree synthesis. However, delays along the scan chain and delays alone the data path of the normal operation mode are different (the former are usually shorter); the clocks determined according to demands of the normal operation functions will cause the scan flip-flops to violate timing specifications of the scan test mode, e.g., to violate hold-time requirement. Similarly, if the clocks of the scan flip-flops are tuned according to timing of the scan test, then the normal operation functions will be influenced. To overcome timing violation of scan flip-flops, a known art is inserting additional delayer buffers along the scan chain, such as the buffers BUFF[1] and BUFF[2] shown in FIG. 1. However, inserting buffers also expands total area of the integrated circuit, degrades integrity of the integrated circuit, increases power consumption, lengthens routing distance, and decreases flexibility of scan reordering (reordering the scan chain).
For satisfying both timing of normal operation and timing of scan chain, IC design flow usually needs to repeat many iterations to seek a balance between timing of normal operation and timing of scan chain, consequently consumes significant design time, cost and resource to insert many buffers to integrated circuit, and sometimes even fails to converge to a result capable of satisfying both timing demands. For advanced fabrication of small dimension, because of shorter delay from the terminals CK to Q, shorter data setup time, greater variation between timing of different chips, and higher uncertainty of clock, influence of hold-time violation becomes severer, and therefore becomes a major challenge of circuit design.
Some prior arts attempt to embed scan chain delay into scan flip-flop, such as U.S. Pat. Nos. 6,389,566, 6,895,540 and 7,649,395. However, these prior arts still suffer disadvantages, such as: number of output terminals incompatible to standard cell, greater layout overhead, lower delay efficiency (delay per unit area) to delay scan chain, and/or failure to correctly operate under low supply voltage utilized in modern advance fabrication process.